H8S2189R Datasheet, PDF (27/812 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series

Figures
Section 1 Overview
Figure 1.1 H8S/2189R Group Internal Block Diagram .................................................................. 2
Figure 1.2 H8S/2189R Group Pin Assignments (TFP-144) ........................................................... 3
Figure 1.3 Sample Design of Reset Signals with no Affection Each Other.................................. 16
Section 2 CPU
Figure 2.1 Exception Vector Table (Normal Mode)..................................................................... 21
Figure 2.2 Stack Structure in Normal Mode ................................................................................. 21
Figure 2.3 Exception Vector Table (Advanced Mode)................................................................. 22
Figure 2.4 Stack Structure in Advanced Mode ............................................................................. 23
Figure 2.5 Memory Map............................................................................................................... 24
Figure 2.6 CPU Internal Registers ................................................................................................ 25
Figure 2.7 Usage of General Registers ......................................................................................... 26
Figure 2.8 Stack............................................................................................................................ 27
Figure 2.9 General Register Data Formats (1).............................................................................. 30
Figure 2.9 General Register Data Formats (2).............................................................................. 31
Figure 2.10 Memory Data Formats............................................................................................... 32
Figure 2.11 Instruction Formats (Examples) ................................................................................ 45
Figure 2.12 Branch Address Specification in Memory Indirect Addressing Mode ...................... 49
Figure 2.13 State Transitions ........................................................................................................ 53
Section 3 MCU Operating Modes
Figure 3.1 Address Map ............................................................................................................... 66
Section 4 Exception Handling
Figure 4.1 Reset Sequence (Mode 2)............................................................................................ 73
Figure 4.2 Stack Status after Exception Handling ........................................................................ 75
Figure 4.3 Operation when SP Value is Odd................................................................................ 76
Section 5 Interrupt Controller
Figure 5.1 Block Diagram of Interrupt Controller........................................................................ 78
Figure 5.2 Relation between IRQ7 and IRQ6 Interrupts, KIN15 to KIN0 Interrupts,
WUE7 to WUE0 Interrupts, KMIMR, KMIMRA, and WUEMRB
(H8S/2140B Group Compatible Vector Mode: EIVS = 0).......................................... 90
Figure 5.3 Relation between IRQ7 and IRQ6 Interrupts, KIN15 to KIN0 Interrupts,
WUE15 to WUE0 Interrupts, KMIMR, KMIMRA, WUEMRB, and WUEMR
(Extended Vector Mode: EIVS = 1) ............................................................................ 91
Figure 5.4 Block Diagram of Interrupts IRQ15 to IRQ0 .............................................................. 95
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