H8S2189R Datasheet, PDF (574/812 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series

Section 15 I²C Bus Interface (IIC)
Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B'11 in
ICXR.
8. Notes on start condition issuance for retransmission
Figure 15.30 shows the timing of start condition issuance for retransmission, and the timing for
subsequently writing data to ICDR, together with the corresponding flowchart. Write the
transmit data to ICDR after the start condition for retransmission is issued and then the start
condition is actually generated.
IRIC = 1?
No
[1]
Yes
Clear IRIC in ICCR
Read SCL pin
SCL = Low?
No
[2]
Yes
Set BBSY = 1,
[3]
SCP = 0 (ICCR)
IRIC = 1?
No
[4]
Yes
Write transmit data to ICDR
[5]
SCL
SDA
9
ACK
[1] Wait for end of 1-byte transfer
[2] Determine whether SCL is low
[3] Issue start condition instruction for retransmission
[4] Determine whether start condition is generated or not
[5] Set transmit data (slave address + R/W)
Note:* Program so that processing from [3] to [5]
is executed continuously.
Start condition generation
(retransmission)
bit7
IRIC
[5] ICDR write (transmit data)
[1] IRIC determination
[4] IRIC determination
[3] (Retransmission) Start condition instruction issuance
[2] Determination of SCL = Low
Figure 15.30 Flowchart for Start Condition Issuance Instruction for Retransmission and
Timing
Rev. 2.00 Aug. 03, 2005 Page 532 of 766
REJ09B0223-0200