H8SX1663 Datasheet, PDF (631/1158 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 10 16-Bit Timer Pulse Unit (TPU)
10.10.9 Conflict between TGR Write and Input Capture
If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture
operation takes precedence and the write to TGR is not performed.
Figure 10.51 shows the timing in this case.
TGR write cycle
T₁
T₂
Pφ
Address
Write
Input capture
signal
TCNT
TGR address
M
TGR
M
Figure 10.51 Conflict between TGR Write and Input Capture
Rev.1.00 Jun. 07, 2006 Page 579 of 1102
REJ09B0294-0100