H8SX1663 Datasheet, PDF (1129/1158 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 25 Electrical Characteristics
25.3.5 Timing of On-Chip Peripheral Modules
Table 25.8 Timing of On-Chip Peripheral Modules
Conditions: V_CC = PLLV_CC = DrV_CC = 3.0 V to 3.6 V, AV_CC = 3.0 V to 3.6 V, V_ref = 3.0 V to AV_CC,
V_SS = PLLV_SS = DrV_SS = AV_SS = 0 V, Pφ = 8 MHz to 35 MHz,
T_a = –20°C to +75°C (regular specifications),
T_a = –40°C to +85°C (wide-range specifications)
Item
Symbol
I/O ports Output data delay time
Input data setup time
Input data hold time
TPU
Timer output delay time
Timer input setup time
Timer clock input setup time
Timer clock Single-edge
pulse width setting
t_PWD
t
PRS
t_PRH
t_TOCD
t_TICS
t_TCKS
t
TCKWH
Both-edge
setting
t_TCKWL
PPG
8-bit
timer
Pulse output delay time
Timer output delay time
Timer reset input setup time
Timer clock input setup time
Timer clock Single-edge
pulse width setting
t
POD
t
TMOD
t_TMRS
t_TMCS
t
TMCWH
Both-edge
setting
t_TMCWL
WDT
SCI
Overflow output delay time t_WOVD
Input clock
cycle
Asynchronous t_Scyc
Clocked
synchronous
Input clock pulse width
t
SCKW
Input clock rise time
t_SCKr
Input clock fall time
t_SCKf
Min.

25
25

25
25
1.5
2.5


25
25
1.5
2.5

4
6
0.4


Max.
40


40



Unit
ns
ns
ns
ns
ns
ns
t
cyc
Test Conditions
Figure 25.39
Figure 25.40
Figure 25.41

t_cyc
40
ns Figure 25.42
40
ns Figure 25.43

ns Figure 25.44

ns Figure 25.45

t
cyc

t_cyc
40
ns Figure 25.46

t_cyc
Figure 25.47

0.6
t
Scyc
1.5
t_cyc
1.5
t_cyc
Rev.1.00 Jun. 07, 2006 Page 1077 of 1102
REJ09B0294-0100