H8SX1663 Datasheet, PDF (272/1158 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 6 Bus Controller (BSC)
6.9.5 Basic Timing
The bus cycle in the address/data multiplexed I/O interface consists of an address cycle and a data
cycle. The data cycle is based on the basic bus interface timing specified by the ABWCR,
ASTCR, WTCRA, WTCRB, RDNCR, and CSACR.
Figures 6.31 and 6.32 show the basic access timings.
Bφ
Address bus
Address cycle
T_ma1
T_ma2
Data cycle
T₁
T₂
CSn
AH
Read
RD
D7 to D0
Write
LLWR
D7 to D0
Address
Address
Read data
Write data
BS
RD/WR
DACK
Note: n = 3 to 7
Figure 6.31 8-Bit Access Space Access Timing (ABWHn = 1, ABWLn = 1)
Rev.1.00 Jun. 07, 2006 Page 220 of 1102
REJ09B0294-0100