H8SX1663 Datasheet, PDF (1017/1158 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 22 Clock Pulse Generator
t_EXH
t_EXL
EXTAL
Vcc × 0.5
t_EXr
t_EXf
Figure 22.5 External Clock Input Timing
22.3 PLL Circuit
The PLL circuit has the function of multiplying the frequency of the clock from the oscillator by a
factor of 4. The frequency multiplication rate is fixed. The phase difference is controlled so that
the timing of the rising edge of the internal clock is the same as that of the EXTAL pin signal.
22.4 Frequency Divider
The frequency divider divides the PLL clock to generate a 1/2, 1/4, or 1/8 clock. After the bits
ICK2 to ICK0, PCK 2 to PCK0, and BCK2 to BCK0 are updated, this LSI operates with the
updated frequency.
22.5 Subclock Oscillator
22.5.1 Connecting 32.768 kHz Crystal Resonator
To supply a clock to the subclock oscillator, connect a 32.768-kHz crystal resonator, as shown in
figure 22.6. The usage notes given in section 22.6.3, Notes on Board Design, apply to the
connection of this crystal resonator.
OSC1
OSC2
C1
C2
C1 = C2 = 15 pF (typ.)
Note: C1 and C2 are reference values that include the floating
capacitance of the board.
Figure 22.6 Connection Example of 32.768-kHz Crystal Resonator
Rev.1.00 Jun. 07, 2006 Page 965 of 1102
REJ09B0294-0100