H8SX1663 Datasheet, PDF (434/1158 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 7 DMA Controller (DMAC)
(3) Activation Timing by DREQ Falling Edge
Figure 7.36 shows an example of single address mode activated by the DREQ signal falling edge.
The DREQ signal is sampled every cycle from the next rising edge of the Bφ signal immediately
after the DTE bit write cycle.
When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is
enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer
request is cleared and starts detecting a high level of the DREQ signal for falling edge detection. If
a high level of the DREQ signal has been detected until completion of the single cycle, receiving
the next transfer request resumes and then a low level of the DREQ signal is detected. This
operation is repeated until the transfer is completed.
Bus
released
DMA single
cycle
Bus
released
DMA single Bus
cycle
released
Bφ
DREQ
Address bus
DACK
DMA
Wait
operation
Channel
Request
Transfer source/
Transfer destination
Single Wait
Duration of transfer
request disabled
Request
Transfer source/
Transfer destination
Single Wait
Duration of transfer
request disabled
Min. of 3 cycles
Min. of 3 cycles
[1]
[2]
[3]
[4]
[5]
[6]
[7]
Transfer request
enable resumed
Transfer request
enable resumed
[1] After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the Bφ signal and a transfer
request is held.
[2][5] The DMAC is activated and the transfer request is cleared.
[3][6] A DMA cycle is started and sampling the DREQ signal at the rising edge of the Bφ signal is started to detect a high level of the
DREQ signal.
[4][7] When a high level of the DREQ signal has been detected, transfer enable is resumed after completion of the write cycle.
(A low level of the DREQ signal is detected at the rising edge of the Bφ signal and a transfer request is held. This is the same as [1].)
Figure 7.36 Example of Transfer in Single Address Mode Activated
by DREQ Falling Edge
Rev.1.00 Jun. 07, 2006 Page 382 of 1102
REJ09B0294-0100