HD49351BP Datasheet, PDF (6/29 Pages) Renesas Technology Corp – CDS/PGA & 10-bit A/D TG Converter

HD49351BP/HBP
Internal Functions
Functional Description
• CDS input
 CCD low-frequency noise is suppressed by CDS (correlated double sampling).
 The signal level is clamped at 14 LSB to 76 LSB (set by resister: 5 bit 2 LSB step controls) during the OB
period. *¹
 Gain can be adjusted using 8 bits of register (0.132 dB steps) within the range from –2.36 dB to 31.40 dB. *²
• ADC input
 The center level of the input signal is clamped at 512 LSB (Typ).
 Gain can be adjusted using 8 bits of register (0.01784 times steps, register settings) within the range from 0.57
times (–4.86 dB) to 5.14 times (14.22 dB). *²
• Automatic offset calibration of PGA and ADC
• DC offset compensation feedback for CCD and CDS
• Pre-blanking
 Digital output is fixed at clamp level
• Digital outputs enable function
Note: 1. It is not covered by warranty when 14 LSB settings
2. Full-scale digital output is defined as 0 dB (one time) when 1 V is input.
Operating Description
Figure 1 shows CDS/PGA + ADC function block.
CDS_in
SP1
SP2
C2
ADC_in
CDS
AMP
PG
AMP
SP1
C1
SH
AMP
Gain setting
(register)
VRT
BLKFB
Current
DAC
BLKSH
BLKC
C4
C3
10bit
ADC
D0 to D9
DAC
Clamp data
(register)
Offset
calibration
logic
DC offset
feedback
logic
OBP
Figure 1 CDS/PGA Functional Block Diagram
1. CDS (Correlated Double Sampling) Circuit
The CDS circuit extracts the voltage differential between the black level and a signal including the black level. The
black level is directly sampled at C1 by using the SP1 pulse, buffered by the SHAMP, then provided to the
CDSAMP.
The signal level is directly sampled at C2 by using the SP2 pulse, and then provided to CDSAMP (see figure 1).
The difference between these two signal levels is extracted by the CDSAMP, which also operates as a
programmable gain amplifier at the previous stage. The CDS input is biased with VRT (2 V). During the PBLK
period, the above sampling and bias operation are paused.
2. PGA Circuit
The PGAMP is the programmable gain amplifier for the latter stage. The PGAMP and the CDSAMP set the gain
using 8 bits of register.
The equation below shows how the gain changes when register value N is from 0 to 255.
In CDSIN mode: Gain = (–2.36 dB + 0.132 dB) × N (LOG linear).
In ADCIN mode: Gain = (0.57 times + 0.001784 times) × N (linear).
Full-scale digital output is defined as 0 dB (one time) when 1 V is input.
Rev.1.0, Jul 06, 2004, page 6 of 28