HD49351BP Datasheet, PDF (10/29 Pages) Renesas Technology Corp – CDS/PGA & 10-bit A/D TG Converter

HD49351BP/HBP
Timing Chart
Figure 2 shows the timing chart when CDS_in and ADC_in input modes are used.
0
1
2
~
9
10
11
• When CDS_in input mode is used
CDS_in
N
N+1
N+2
N+9
N+10
N+11
SP1
SP2
ADCLK
D0 to D9
N−10
N−9
N−8
N−1
N
• When ADC_in input mode is used
N
ADC_in
N+1
N+2
ADCLK
D0 to D9
N−9
N−8
N+10
N+11
N+8
N+9
N−1
N
N+1
Figure 2 Output Timing Chart when CDS_in and ADC_in Input Modes are Used
• The ADC output (D0 to D9) is output at the rising edge of the ADCLK in both modes.
• Pipe-line delay is ten clock cycles when CDS_in is used and nine when ADC_in is used.
• In ADC_in input mode, the input signal is sampled at the rising edge of the ADCLK.
Rev.1.0, Jul 06, 2004, page 10 of 28