HD49351BP Datasheet, PDF (14/29 Pages) Renesas Technology Corp – CDS/PGA & 10-bit A/D TG Converter

HD49351BP/HBP
Absolute Maximum Ratings
Item
Symbol
Ratings
Power supply voltage
Vdd(max)
4.1
Power dissipation
Pt(max)
500
Operating power supply voltage
Vopr
2.70 to 3.45
Analog input voltage
VIN(max)
–0.3 to AVdd +0.3
Digital input voltage
Operating temperature
VI(max)
Topr
–0.3 to DVdd +0.3
–10 to +75
Storage temperature
Tstg
–55 to +125
Note: AVdd, AVss are analog power source systems of CDS, PGA, and ADC.
DVdd1, DVss1 are digital power source systems of CDS, PGA and ADC.
DVdd2, DVss2 are buffer power source systems of ADC output.
DVdd3, DVss3 are general digital power source systems of TG.
DVdd4, DVss4 are buffer power source systems of H1 and H2.
• Pin 2 multi bonds the DVss1 and DVss2
• When pin 64 is set to Low, pin 41 = STROB output, pin 39 = SUB_SW output
When Hi, pin 41 = Vgate input, pin 39 = ADCLK input
(Ta = 25°C)
Unit
V
mW
V
V
V
°C
°C
Electrical Characteristics
(Unless specified, Ta = 25°C, AVdd = 3.0 V, DVdd = 3.0 V, and R_BIAS = 33 kΩ)
• Items Common to CDS_in and ADC_in Input Modes
Item
Symbol Min
Typ
Max
Unit
Test Conditions Remarks
Power supply voltage
Vdd
2.70
3.00
3.45
V
range
Conversion frequency
Digital input voltage
fCLK hi
fCLK low
V_IH2
VIL2
20
—
5.5
—
2.25
×
DVdd
3.0
—
0
—
36
25
DVdd
MHz
MHz
V
0.6
×
DVdd
3.0
V
LoPwr = low *¹
LoPwr = high
HD49351HBP
HD49351BP
All of digital input
pin
Digital output voltage
VOH
DVdd –0.5 —
—
VOL
—
—
0.5
Digital input current
I_IH
—
—
50
IIL
–50
—
—
Digital output current
IOZH
—
—
50
IOZL
–50
—
—
ADC resolution
RES
—
10
—
V
IOH = –1 mA
V
IOL = +1 mA
µA
DVdd = V_IH = 3.0 V
µA
VIL = 0 V
µA
VOH = Vdd
µA
VOL = 0 V
bit
ADC integral linearity
ADC differential linearity
Sleep current
INL
DNL
ISLP
—
—
–100
(2)
—
(±0.3)
—
0
100
LSBp-p fCLK = 20 MHz
LSB
f_CLK = 20 MHz
*2
µA
Fix digital input pin
to 0 V, output pin
should open
Standby current
ISTBY
—
3
5
mA
Fix digital I/O pin to
0V
Digital output Hi-Z delay tHZ
—
time
tLZ
—
t_ZH
—
tZL
—
—
100
—
100
—
100
—
100
ns
RL = 2 kΩ,
ns
C_L = 10 pF
ns
ns
Refer to figure 7
Notes: 1. It is expressing on the frequency in an analog circuit part. Please keep in your mind that TG part has 2
divided, 3 divided mode.
2. Differential linearity is the calculated difference in linearity errors between adjacent codes.
3. Values within parentheses ( ) are for reference.
Rev.1.0, Jul 06, 2004, page 14 of 28