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HD49351BP Datasheet, PDF (19/29 Pages) Renesas Technology Corp – CDS/PGA & 10-bit A/D TG Converter
HD49351BP/HBP
Address
STD1[7:0] (L)
1 1 1 1 0 1 0 0 D7 D6 D5 D4 D3 D2 D1 D0
STD2[15:8] (H)
D12 D11 D10 D9 D8
VD latch H12_Buff
MON
Gray_test
• MON (D0 to D2 of address H’F4)
Select the pulse which output to pin MON (pin 60).
When D0 to D2: 0, Fix to Low
When 1, ADCLK
When 2, SP1
When 3, SP2
When 4, OBP
When 5, PBLK
When 6, CPDM
When 7, DLL_test
• H12Baff (D3 to D6 of address H’F4)
Select the buffer size which output to pin H1A, H2A (pin 22, 26).
D3: 2 mA buffer
D4: 4 mA buffer
D5: 10 mA buffer
D6: 14 mA buffer
Above data can be on/off individually. Default is D6 can be on only. (18 mA buffer)
• VD latch (D7 of address H’F4)
Data = 0: Gain data is determined when CS rising
Data = 1: Gain data is determined when VD rising
• Gray (D8 to D9 of address H’F4)
ADC output code can be change to following types. Differential code is mentioned to next page.
Gray Code [1] Gray Code [0] Output Code
0
0
Binary code
0
1
Gray code
1
0
Differential encoded binary
1
1
Differential encoded gray
Gray code
• Gray_test (D10 to D12 of address H’F4)
Data which determine the differential code and standard phase of gray code.
Rev.1.0, Jul 06, 2004, page 19 of 28