HD49351BP Datasheet, PDF (27/29 Pages) Renesas Technology Corp – CDS/PGA & 10-bit A/D TG Converter

HD49351BP/HBP
• CDS single operating mode
Pin 56(Test2 = Low) ∗Pin 57 is "Don't care" in this mode.
3.0V
47µ
47/6 ⁺ 0.1
47µ
Reset(Normally Hi)
0.1
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
ADC_in
33k
0.1
0.1
0.1
47µ
33
34
35
36 PBLK
37 OBP
38 CP_DM
39 ADCK
40 SP2
41 SP1
42 DV_SS3
43 AV_SS
44 ADC_in
45 BIAS
46 VRB
47 VRT
48 VRM
HD49351
16
15
DV_SS3 14
DV_DD2 13
D9 12
D8 11
D7 10
D6 9
D5 8
D4 7
D3 6
D2 5
D1 4
D0 3
DV_SS1,2 2
1
AV_DD
SCK
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
+
0.1
47/6
1µ 1µ
0.1
to
Camera
signal
processor
∗Pin changes are not effective with pin 61.
47/6
1000p
CCD signal input
100p
Serial data input
Unit: R: Ω
C: F
Serial data when CDS single operation mode are following resister specifications.
(Latch timing specification is same as normal mode)
CS
fsck
t_INT1
t_INT2
SCK
tsu
tho
SDATA
D00 D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15
Resister 0
Resister 1
Resister 2
D00
Low
0 High 1
Low
0
D01
Low
0
Low
0 High 1
D02
Low
0
Low
0
Low
0
D03
X
0
SLP
Low: Normal
High: Sleep
0
Clamp(0)
1
D04
X
0
STBY
Low: Normal
High: Standby
0
Clamp(1)
0
D05 PGA(0) LSB 0 Output mode(LINV) 0 Clamp(2)
0
D06 PGA(1)
0 Output mode(MINV) 0 Clamp(3)
1
D07 PGA(2)
0 Output mode(Test0) 0 Clamp(4)
0
D08 PGA(3)
0 SHA-fsel(0) 0 HGstop-Hsel(0) 0
D09 PGA(4)
0 SHA-fsel(1) 0 HGstop-Hsel(1) 0
D10 PGA(5)
0 SHSW-fsel(0) 0 HGain-Nsel(0) 0
D11 PGA(6)
D12 PGA(7) MSB
D13 Test_I1 (0)
D14 Test_I1 (1)
D15 Test_I1 (2)
0 SHSW-fsel(1)
0 SHSW-fsel(2)
0 SHSW-fsel(3)
0 Test_I2 (0)
1 Test_I2 (1)
0 HGain-Nsel(1) 0
0
LoPwr
Low: Normal
High: Low power
1
0
X
0
0
ADSEL
Low:CDSin
High:ADin
0
0
Reset
Low: Reset
High: Normal
1
Resister 3
Resister 4
Resister 5
Resister 6
Resister 7
High 1 Low 0 High 1 Low 0 High 1
High 1 Low 0 Low 0 High 1 High 1
Low 0 High 1 High 1 High 1 High 1
0 MON(0)
0 P_SP1(0)
1 DL_SP1(0) 0 DL_RG_r(0) 0
0 MON(1)
0 P_SP1(1)
0 DL_SP1(1) 0 DL_RG_r(1) 0
0 MON(2)
0 P_SP2(0)
1 DL_SP1(2) 0 DL_RG_r(2) 0
0 H12Baff(0) 0 P_SP2(1)
1 DL_SP1(3) 0 DL_RG_r(3) 0
0 H12Baff(1) 0 P_ADCLK(0) 1 DL_SP2(0) 0 DL_RG_f(0) 0
0 H12Baff(2) 0 P_ADCLK(1) 0 DL_SP2(1) 0 DL_RG_f(1) 1
test
0 H12Baff(3)
1 P_RG(0)
0 DL_SP2(2) 0 DL_RG_f(2) 0
0 VD latch
0 P_RG(1)
0 DL_SP2(3) 0 DL_RG_f(3) 1
0 Gray1
0 DLL_CK(0) 1 DL_ADCLK(0) 0 DMCG(0)
0
0 Gray2
0 DLL_CK(1) 0 DL_ADCLK(1) 0 DMCG(1)
0
0 Gray_ts(0) 0 DLL_CK(2) 1 DL_ADCLK(2) 0 Dummy CP(0) 0
0 Gray_ts(1) 0 DLL_CK(3) 1 DL_ADCLK(3) 0 Dummy CP(1) 0
0 Gray_ts(2) 0 DLL_current 1 CDS_test
0 Dummy CP(2) 0
Rev.1.0, Jul 06, 2004, page 27 of 28