7751 Datasheet, PDF (526/540 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER

APPENDIX
Appendix 9. Q & A
Interrupt
Q
____
(1)
Which
timing
of
clock
φ1
is
the
external
interrupts
(input signals
____
to
the
INTi
pin)
detected?
(2) How can four or more external interrupt input pins (INTi) be used?
A
(1) In both the edge sense and level sense, external interrupt requests occur when the input
____
signal to the INTi pin changes its level regardless of clock φ1.
In the edge sense, the interrupt request bit is set to “1” at this time.
(2) There are two methods: one uses external interrupt’s level sense, and the other uses the
timer’s event counter mode.
Œ Using external interrupt’s level sense
____
In hardware, input a logical sum of multiple interrupt signals (e.g., ‘a’, ‘b’, and ‘c’) to the INTi
pin, and input each signal to each corresponding port.
___
In software, check the port’s input levels in the INTi interrupt routine to determine that which
of the signals ‘a’, ‘b’, and ‘c’ is input.
M37751
Port
Port
Port
INTi
 Using timer’s event counter mode
In hardware, input interrupt signals to the TAiIN pins or TBiIN pins.
In software, set the timer’s operating mode to the event counter mode and a value “000016”
into the timer register to the effective edge.
The timer’s interrupt request occurs when an interrupt signal (selected effective edge) is input.
7751 Group User’s Manual
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