7751 Datasheet, PDF (189/540 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER

SERIAL I/O
7.3 Clock synchronous serial I/O mode
Receive enable bit ^{“1”}
“0”
“1”
Transmit enable bit
“0”
Dummy data is set to UARTi transmit buffer register.
Transmit buffer ^{“1”}
empty flag
“0”
“H”
RTSi
“L”
1/fEXT
UARTi transmit register¨← UARTi transmit buffer register
CLKi
Received data taken in
RxDi
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5
“1”
Receive complete flag
“0”
UARTi receive register → UARTi receive buffer register
UARTi receive buffer register is read out.
UARTi receive ^{“1”}
interrupt request bit _{“0”}
The above timing diagram applies to the following
setting conditions:
q External clock selected.
q RTS function selected.
fEXT: Frequency of external clock
Cleared to “0” when interrupt request is accepted or
cleared by software.
: When the CLKi pin’s input level is “H,” satisfy the
following cinditions:
q Transmit enable bit → “1”
q Receive enable bit → “1”
q Writing of dummy data to UARTi transmit
buffer register
Fig. 7.3.11 Example of receive timing (when selecting external clock)
7–32
7751 Group User’s Manual