TMS320C6474 Datasheet, PDF (5/204 Pages) Texas Instruments – Multicore Digital Signal Processor

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TMS320C6474
Multicore Digital Signal Processor
SPRS552 – OCTOBER 2008
1.3 C6474 Functional Block Diagram
Figure 1-2 shows the functional block diagram of the C6474 device.
32
DDR2 Memory
Controller
PLL2
2
Serial RapidIO
(2x)
TCP2
VCP2
McBSP0
McBSP1
EMAC
10/100/1000
SGMII
MDIO
I2C
16
GPIO16
FSYNC
Antenna
Interface
Timer [0-5]
DSP Subsystem 2
DSP Subsystem 1
DSP Subsystem 0
32K Bytes
L1P SRAM/Cache
Direct-Mapped
L2/Cache
0.5 - 1.5 M
C64x+ Megamodule
L1P Memory Controller (Memory Protect/Bandwidth Mgmt)
C64x+ DSP Core
Instruction Fetch
16-/32-bit
Instruction Dispatch
Control Registers
SPLOOP Buffer
Instruction Decode
In-Circuit Emulation
A Register File
A31 - A16
A15 - A0
B Register File
B31 - B16
B15 - B0
.M1
.L1 .S1 xx .D1
xx
.M2
.D2 xx .S2 .L2
xx
L1 Data Memory Controller (Memory Protect/Bandwidth Mgmt)
32K Bytes Total
L1D SRAM/Cache 2-Way
Set Associative
EDMA 3.0
L3 ROM
Semaphore
PLL1 and
PLL1 Controller
Power-Down and Device
Configuration Logic
Boot Configuration
Figure 1-2. Functional Block Diagram
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Features
5