TMS320C6474 Datasheet, PDF (121/204 Pages) Texas Instruments – Multicore Digital Signal Processor

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TMS320C6474
Multicore Digital Signal Processor
SPRS552 – OCTOBER 2008
7.7.3.7 PLL Controller Status Register
The PLL controller status register (PLLSTAT) shows the PLL controller status. PLLSTAT is shown in
Figure 7-17 and described in Table 7-27.
31
16
Reserved
R-0
15
1
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 7-17. PLL Controller Status Register (PLLSTAT) [Hex Address: 029A 013C]
0
GOSTAT
R-0
Table 7-27. PLL Controller Status Register (PLLSTAT) Field Descriptions
Bit Field
31:1 Reserved
0 GOSTAT
Value
0
0
1
Description
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
GO operation status.
GO operation is not in progress. SYSCLK divide ratios are not being changed.
GO operation is in progress. SYSCLK divide ratios are being changed.
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Peripheral Information and Electrical Specifications 121