TMS320C6474 Datasheet, PDF (190/204 Pages) Texas Instruments – Multicore Digital Signal Processor

TMS320C6474
Multicore Digital Signal Processor
SPRS552 – OCTOBER 2008
www.ti.com
Table 7-78. Antenna Interface System Registers (continued)
HEX ADDRESS
02BE AA00 - 02BE AB4C
02BE AB50 - 02BE ABFC
02BE AC00 - 02BE AC50
02BE AC54 - 02BE ACFC
02BE AD00 - 02BE AD50
02BE AD54 - 02BE AFFC
02BE B000
02BE B004 -02BE FFFC
02BF 0000
02BF 0004
02BF 0008
02BF 000C
02BF 0010
02BF 0014
02BF 0018
02BF 001C
02BF 0020
02BF 0024
02BF 0028
02BF 002C
02BF 0030
02BF 0034
02BF 0038 - 02BF 07FC
02BF 0800
02BF 0804
02BF 0808
02BF 080C
02BF 0810
02BF 0814
02BF 0818
02BF 081C
02BF 0820
02BF 0824
ACRONYM
PE_LINK5_84CNT_LUT
-
PE_LINK5_ID_LUT0
-
PE_LINK5_ID_LUT1
-
PE_CFG
-
EE_LINK0_IRS_A
EE_LINK0_IRS_B
EE_LINK0_IMS_A_EV0
EE_LINK0_IMS_B_EV0
EE_LINK0_IMS_A_EV1
EE_LINK0_IMS_B_EV1
EE_LINK0_MSK_SET_A_EV0
EE_LINK0_MSK_SET_B_EV0
EE_LINK0_MSK_SET_A_EV1
EE_LINK0_MSK_SET_B_EV1
EE_LINK0_MSK_CLR_A_EV0
EE_LINK0_MSK_CLR_B_EV0
EE_LINK0_MSK_CLR_A_EV1
EE_LINK0_MSK_CLR_B_EV1
-
EE_LINK1_IRS_A
EE_LINK1_IRS_B
EE_LINK1_IMS_A_EV0
EE_LINK1_IMS_B_EV0
EE_LINK1_IMS_A_EV1
EE_LINK1_IMS_B_EV1
EE_LINK1_MSK_SET_A_EV0
EE_LINK1_MSK_SET_B_EV0
EE_LINK1_MSK_SET_A_EV1
EE_LINK1_MSK_SET_B_EV1
REGISTER NAME
PE 84 Count LUT RAM
Reserved
PE Identity LUT Part 0 RAM
Reserved
PE Identity LUT Part 1 RAM
Reserved
Protocol Encoder Configuration Register
Reserved
EE Link 0 Interrupt Source Raw Status Register A
EE Link 0 Interrupt Source Raw Status Register B
EE Link 0 AI_EVENT[0] Interrupt Source Masked Status
Register A
EE Link 0 AI_EVENT[0] Interrupt Source Masked Status
Register B
EE Link 0 AI_EVENT[1] Interrupt Source Masked Status
Register A
EE Link 0 AI_EVENT[1] Interrupt Source Masked Status
Register B
EE Link 0 AI_EVENT[0] Interrupt Source Mask Set
Register A
EE Link 0 AI_EVENT[0] Interrupt Source Mask Set
Register B
EE Link 0 AI_EVENT[1] Interrupt Source Mask Set
Register A
EE Link 0 AI_EVENT[1] Interrupt Source Mask Set
Register B
EE Link 0 AI_EVENT[0] Interrupt Source Mask Clear
Register A
EE Link 0 AI_EVENT[0] Interrupt Source Mask
ClearRegister B
EE Link 0 AI_EVENT[1] Interrupt Source Mask Clear
Register A
EE Link 0 AI_EVENT[1] Interrupt Source Mask Clear
Register B
Reserved
EE Link 1 Interrupt Source Raw Status Register A
EE Link 1 Interrupt Source Raw Status Register B
EE Link 1 AI_EVENT[0] Interrupt Source Masked Status
Register A
EE Link 1 AI_EVENT[0] Interrupt Source Masked Status
Register B
EE Link 1 AI_EVENT[1] Interrupt Source Masked Status
Register A
EE Link 1 AI_EVENT[1] Interrupt Source Masked Status
Register B
EE Link 1 AI_EVENT[0] Interrupt Source Mask Set
Register A
EE Link 1 AI_EVENT[0] Interrupt Source Mask Set
Register B
EE Link 1 AI_EVENT[1] Interrupt Source Mask Set
Register A
EE Link 1 AI_EVENT[1] Interrupt Source Mask Set
RegisterB
190 Peripheral Information and Electrical Specifications
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