HAT1097R Datasheet, PDF (5/8 Pages) Renesas Technology Corp – Silicon P Channel Power MOS FET High Speed Power Switching

HAT1097R, HAT1097RJ
Reverse Drain Current vs.
Source to Drain Voltage
–10
–8
–10 V
Pulse Test
–6
–4
–5 V
V_GS = 0, 5 V
–2
0
0 –0.4 –0.8 –1.2 –1.6 –2.0
Source Drain Voltage V_SD (V)
Avalanche Test Circuit
Vin
-15 V
V DS
Monitor
Rg
50 Ω
L
I AP
Monitor
D. U. T
VDD
Switching Time Test Circuit
Vin Monitor
Rg
D.U.T.
Vout
Monitor
R_L
Vin
-10 V
VDD
= -30 V
Maximum Avalanche Energy vs.
Channel Temperature Derating
2.5
I _AP = −5 A
2.0
V _DD = −25 V
duty < 0.1 %
Rg > 50 Ω
1.5
1.0
0.5
0
25 50 75 100 125 150
Channel Temperature Tch (°C)
Avalanche Waveform
E_AR =
1
2
L•
I
2
AP
•
V_DSS
V_DSS - V _DD
I _AP
I_D
V_(BR)DSS
V_DS
VDD
0
Switching Time Waveform
Vin
10%
90%
90%
90%
Vout
td(on)
10%
tr
td(off)
10%
t_f
Rev.1.00, Feb.15.2005, page 5 of 7