H8-3067 Datasheet, PDF (439/963 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 10 8-Bit Timers
Clear by Compare Match: Depending on the setting of the CCLR1 and CCLR0 bits in TCR,
TCNT can be cleared when compare match A or B occurs, Figure 10.11 shows the timing of this
operation.
φ
Compare match signal
TCNT
N
H'00
Figure 10.11 Timing of Clear by Compare Match
Clear by Input Capture: Depending on the setting of the CCLR1 and CCLR0 bits in TCR,
TCNT can be cleared when input capture B occurs. Figure 10.12 shows the timing of this
operation.
φ
Input capture input
Input capture signal
TCNT
N
H '00
Figure 10.12 Timing of Clear by Input Capture
10.4.3 Input Capture Signal Timing
Input capture on the rising edge, falling edge, or both edges can be selected by settings in TCSR.
Figure 10.13 shows the timing when the rising edge is selected.
The pulse width of the input capture input signal must be at least 1.5 system clocks when a single
edge is selected, and at least 2.5 system clocks when both edges are selected.
Rev. 4.00 Jan 26, 2006 page 417 of 938
REJ09B0276-0400