H8-3067 Datasheet, PDF (203/963 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 6 Bus Controller
φ
RTCNT
N
H'00
RTCOR
N
Refresh request signal
and CMF bit setting signal
Figure 6.27 Compare Match Timing
TRp
TR1
TR2
φ
Address bus*
CSn(RAS)
PB₄/PB₅
(UCAS/LCAS)
RD(WE)
RFSH
Area 2 start address
High
AS
High level
Note: * In address update mode 1, the area 2 start address is output.
In address update mode 2, the address in the preceding bus cycle is retained.
Figure 6.28 CBR Refresh Timing (CSEL = 0, TPC = 0, RLW = 0)
Rev. 4.00 Jan 26, 2006 page 181 of 938
REJ09B0276-0400