H8-3067 Datasheet, PDF (211/963 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 6 Bus Controller
• In the event of contention with a bus request from an external bus master when a transition is
made to software standby mode, the BACK and strobe states may be indeterminate after the
transition to software standby mode (see figure 6.36).
When software standby mode is used, the BRLE bit should be cleared to 0 in BRCR before
executing the SLEEP instruction.
Similar contention in a transition to self-refresh mode may prevent dependable strobe
waveform output. This can also be avoided by clearing the BRLW bit to 0 in BRCR.
• Immediately after self-refreshing is cleared, external bus release is possible during a given
period until the start of a CPU cycle. Attention must be paid to the RAS state to ensure that the
specification for the RAS precharge time immediately after self-refreshing is met.
External bus released
φ
Refresh cycle
CPU cycle
Refresh cycle
RFSH
Refresh
request
BACK
Figure 6.35 Bus-Released State and Refresh Cycles
Rev. 4.00 Jan 26, 2006 page 189 of 938
REJ09B0276-0400