H8-3067 Datasheet, PDF (17/963 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

14.3.6 Transmitting and Receiving Data ........................................................................ 558
14.4 Usage Notes ...................................................................................................................... 566
Section 15 A/D Converter................................................................................................. 569
15.1 Overview........................................................................................................................... 569
15.1.1 Features................................................................................................................ 569
15.1.2 Block Diagram ..................................................................................................... 570
15.1.3 Input Pins ............................................................................................................. 571
15.1.4 Register Configuration......................................................................................... 572
15.2 Register Descriptions ........................................................................................................ 573
15.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 573
15.2.2 A/D Control/Status Register (ADCSR) ............................................................... 574
15.2.3 A/D Control Register (ADCR) ............................................................................ 577
15.3 CPU Interface.................................................................................................................... 578
15.4 Operation .......................................................................................................................... 580
15.4.1 Single Mode (SCAN = 0) .................................................................................... 580
15.4.2 Scan Mode (SCAN = 1)....................................................................................... 582
15.4.3 Input Sampling and A/D Conversion Time ......................................................... 584
15.4.4 External Trigger Input Timing............................................................................. 586
15.5 Interrupts ........................................................................................................................... 587
15.6 Usage Notes ...................................................................................................................... 587
Section 16 D/A Converter................................................................................................. 593
16.1 Overview........................................................................................................................... 593
16.1.1 Features................................................................................................................ 593
16.1.2 Block Diagram ..................................................................................................... 594
16.1.3 Input/Output Pins ................................................................................................. 594
16.1.4 Register Configuration......................................................................................... 595
16.2 Register Descriptions ........................................................................................................ 596
16.2.1 D/A Data Registers 0 and 1 (DADR0/1).............................................................. 596
16.2.2 D/A Control Register (DACR) ............................................................................ 596
16.2.3 D/A Standby Control Register (DASTCR).......................................................... 598
16.3 Operation .......................................................................................................................... 599
16.4 D/A Output Control .......................................................................................................... 600
Section 17 RAM .................................................................................................................. 601
17.1 Overview........................................................................................................................... 601
17.1.1 Block Diagram ..................................................................................................... 602
17.1.2 Register Configuration......................................................................................... 603
17.2 System Control Register (SYSCR) ................................................................................... 604
17.3 Operation .......................................................................................................................... 605
Rev. 4.00 Jan 26, 2006 page xvii of xxii