H8S2268 Datasheet, PDF (393/725 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

Section 13 Serial Communication Interface (SCI)
Table 13.3 shows sample N settings in BRR in normal asynchronous mode. Table 13.4 shows the
maximum bit rate for each frequency in normal asynchronous mode. Table 13.6 shows sample N
settings in BRR in clocked synchronous mode. Table 13.8 shows sample N settings in BRR in
Smart Card interface mode. In Smart Card interface mode, S (the number of basic clock periods in
a 1-bit transfer interval) can be selected. For details, refer to section 13.7.4, Receive Data
Sampling Timing and Reception Margin. Tables 13.5 and 13.7 show the maximum bit rates with
external clock input.
When the ABCS bit in SEMR_0 of SCI_0 is set to 1 in asynchronous mode, the maximum bit rate
is twice the value shown in tables 13.4 and 13.5.
Table 13.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (1)
Bit Rate
(bps) n
110
1
150
1
300
0
600
0
1200 0
2400 0
4800 0
9600 
19200 
31250 0
38400 
2
Error
N (%)
141 0.03
103 0.16
207 0.16
103 0.16
51 0.16
25 0.16
12 0.16


1 0.00

Operating Frequency φ (MHz)
2.097152
2.4576
Error
n N (%)
nN
Error
(%)
1 148 –0.04 1 174 –0.26
1 108 0.21
1 127 0.00
0 217 0.21
0 255 0.00
0 108 0.21
0 127 0.00
0 54 –0.70 0 63 0.00
0 26 1.14
0 31 0.00
0 13 –2.48 0 15 0.00
0 6 –2.48 0 7
0.00

03
0.00

 

01
0.00
3
n N Error (%)
1 212 0.33
1 155 0.16
1 77 0.16
0 155 0.16
0 77 0.16
0 38 0.16
0 19 –2.34
09
–2.34
04
–2.34
02
0.00
 
Rev. 4.00 Mar 21, 2006 page 325 of 654
REJ09B0071-0400