H8S2268 Datasheet, PDF (127/725 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

Section 4 Exception Handling
Section 4 Exception Handling
4.1 Exception Handling Types and Priority
As table 4.1 indicates, exception handling may be caused by a reset, trace*, trap instruction, or
interrupt. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur
simultaneously, they are accepted and processed in order of priority. Trap instruction exception
handling requests are accepted at all times in program execution state.
Exception sources, the stack structure, and operation of the CPU vary depending on the interrupt
control mode set by the INTM0 and INTM1 bits in SYSCR.
Table 4.1 Exception Types and Priority
Priority Exception Type
Start of Exception Handling
High
Reset
Trace^*
Starts immediately after a low-to-high transition at the RES pin,
or when the watchdog timer overflows. The CPU enters the
reset state when the RES pin is low.
Starts when execution of the current instruction or exception
handling ends, if the trace (T) bit in the EXR is set to 1. Traces
are enabled only in interrupt control mode 2. Trace exception
handling is not executed after execution of an RTE instruction.
Interrupt
Starts when execution of the current instruction or exception
handling ends, if an interrupt request has been issued. Interrupt
detection is not performed on completion of ANDC, ORC,
XORC, or LDC instruction execution, or on completion of reset
exception handling.
Trap instruction
Low
Started by execution of a trap instruction (TRAPA). Trap
instruction exception handling requests are accepted at all times
in program execution state.
Note: * Supported only by the H8S/2268 Group.
Rev. 4.00 Mar 21, 2006 page 59 of 654
REJ09B0071-0400