H8S2268 Datasheet, PDF (313/725 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

φ
Address
Status flag
Section 10 16-Bit Timer Pulse Unit (TPU)
DTC
read cycle
T1
T2
DTC
write cycle
T1
T2
Source address
Destination
address
Interrupt
request
signal
Figure 10.44 Timing for Status Flag Clearing by DTC Activation (H8S/2268 Group Only)
10.10 Usage Notes
10.10.1 Module Stop Mode Setting
TPU operation can be disabled or enabled using the module stop control register. The initial
setting is for TPU operation to be halted. Register access is enabled by clearing module stop
mode. For details, refer to section 22, Power-Down Modes.
10.10.2 Input Clock Restrictions
The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at
least 2.5 states in the case of both-edge detection. The TPU will not operate properly at narrower
pulse widths.
In the H8S/2268 Group phase counting mode, the phase difference and overlap between the two
input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. Figure
10.45 shows the input clock conditions in phase counting mode.
Rev. 4.00 Mar 21, 2006 page 245 of 654
REJ09B0071-0400