H8S2268 Datasheet, PDF (320/725 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

Section 10 16-Bit Timer Pulse Unit (TPU)
10.10.10 Contention between Buffer Register Write and Input Capture (H8S/2268 Group
Only)
If an input capture signal is generated in the T2 state of a buffer register write cycle, the buffer
operation takes precedence and the write to the buffer register is not performed.
Figure 10.52 shows the timing in this case.
φ
Address
Write signal
Input capture
signal
TCNT
Buffer register write cycle
T1
T2
Buffer register
address
N
TGR
M
N
Buffer
M
register
Figure 10.52 Contention between Buffer Register Write and Input Capture
Rev. 4.00 Mar 21, 2006 page 252 of 654
REJ09B0071-0400