H8S2268 Datasheet, PDF (369/725 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

Section 13 Serial Communication Interface (SCI)
Section 13 Serial Communication Interface (SCI)
This LSI has three independent serial communication interface (SCI) channels. The SCI can
handle both asynchronous and clocked synchronous serial communication. Serial data
communication can be carried out using standard asynchronous communication chips such as a
Universal Asynchronous Receiver/Transmitter (UART) or an Asynchronous Communication
Interface Adapter (ACIA). A function is also provided for serial communication between
processors (multiprocessor communication function). The SCI also supports an IC card (Smart
Card) interface conforming to ISO/IEC 7816-3 (Identification Card) as a serial communication
interface extension function.
13.1 Features
• Choice of asynchronous or clocked synchronous serial communication mode
• Full-duplex communication capability
The transmitter and receiver are mutually independent, enabling transmission and reception to
be executed simultaneously.
Double-buffering is used in both the transmitter and the receiver, enabling continuous
transmission and continuous reception of serial data.
• On-chip baud rate generator allows any bit rate to be selected
External clock can be selected as a transfer clock source (except for in Smart Card interface
mode).
• Choice of LSB-first or MSB-first transfer (except in the case of asynchronous mode 7-bit data)
• Four interrupt sources
Transmit-end, transmit-data-empty, receive-data-full, and receive error  that can issue
requests.
The transmit-data-empty interrupt and receive data full interrupts can be used to activate the
data transfer controller (DTC) (H8S/2268 Group only).
• Module stop mode can be set
Asynchronous Mode
• Data length: 7 or 8 bits
• Stop bit length: 1 or 2 bits
• Parity: Even, odd, or none
• Receive error detection: Parity, overrun, and framing errors
• Break detection: Break can be detected by reading the RxD pin level directly in the case of a
framing error
SCI0025B_000020020700
Rev. 4.00 Mar 21, 2006 page 301 of 654
REJ09B0071-0400