H8S2268 Datasheet, PDF (129/725 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

Section 4 Exception Handling
Exception Source
Vector Number Vector Address Advanced Mode^*1
Internal interrupt^*2
24
H'0060 to H'0063


107
H'01AC to H'01AF
External interrupt WKP0 to WKP7 108
H'01B0 to H'01B3
Internal interrupt
120
H'01E0 to H'01E3


123
H'01EC to H'01EF
Notes: 1. Lower 16 bits of the address.
2. For details of internal interrupt vectors, see section 5.4.3, Interrupt Exception Handling
Vector Table.
3. For details on direct transitions, see section 22.10, Direct Transitions.
4. Supported only by the H8S/2268 Group.
4.3 Reset
A reset has the highest exception priority.
When the RES pin goes low, all processing halts and this LSI enters the reset. A reset initializes
the internal state of the CPU and the registers of on-chip peripheral modules. The interrupt control
mode is 0 immediately after reset.
When the RES pin goes high from the low state, this LSI starts reset exception handling.
The chip can also be reset by overflow of the watchdog timer. For details see section 12,
Watchdog Timer (WDT).
4.3.1 Reset Exception Handling
When the RES pin goes low, this LSI enters the reset. To ensure that this LSI is reset, hold the
RES pin low for at least 20 ms at power-up. To reset the chip during operation, hold the RES pin
low for at least 20 states. When the RES pin goes high after being held low for the necessary time,
this LSI starts reset exception handling as follows.
1. The internal state of the CPU and the registers of the on-chip peripheral modules are
initialized, the T bit in EXR* is cleared to 0, and the I bits in EXR* and CCR is set to 1.
2. The reset exception handling vector address is read and transferred to the PC, and program
execution starts from the address indicated by the PC.
Note: * Supported only by the H8S/2268 Group.
Rev. 4.00 Mar 21, 2006 page 61 of 654
REJ09B0071-0400