M37544 Datasheet, PDF (39/68 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

7544 Group
Stop mode
Wait mode
Interrupt
STP
instruction
Interrupt
WIT
instruction
WIT
instruction
Interrupt
State 1
Operation clock source:
f(XIN) (Note 1)
f(XIN) oscillation enabled
On-chip oscillator stop
State 2
CPUM3←02 _{Operation clock source:}
f(XIN) (Note 1)
f(XIN) oscillation enabled
CPUM3¨12 On-chip oscillator enabled
MISRG1¨12
MISRG1←02
CPUM76¨102
State 3
Operation clock source:
State 4
CPUM4←12 _{Operation clock source:}
On-chip oscillator (Note 3)
On-chip oscillator (Note 3)
f(XIN) oscillation enabled
On-chip oscillator enabled
CPUM76¨002
012
112
(Note 2)
f(XIN) oscillation stop
CPUM4¨02 _{On-chip oscillator enabled}
Notes on switch of clock
(1) In operation clock source = f(XIN), the following can be
MISRG1¨12
MISRG1¨02
selected for the CPU clock division ratio.
● f(XIN)/2 (high-speed mode)
● f(XIN)/8 (middle-speed mode)
State 2’
Operation clock source:
CPUM76¨102
State 3’
Operation clock source:
f(XIN) (Note 1)
On-chip oscillator (Note 3)
f(XIN) oscillation enabled
On-chip oscillator enabled
f(XIN) oscillation enabled
CPUM76←002
012
On-chip oscillator enabled
112
(Note 2)
Oscillation stop detection circuit valid
Reset released
● f(XIN) (double-speed mode, only at a ceramic/quartz-crystal
oscillation)
(2) Execute the state transition state 3 to state 2 or
state 3’ to state 2’ after stabilizing XIN oscillation.
(3) In operation clock source = on-chip oscillator, the middle-
speed mode is selected for the CPU clock division ratio.
(4) When the state transition state 2 → state 3 → state 4
is performed, execute the NOP instruction as shown below
according to the division ratio of CPU clock.
Reset state
• CPUM76 → 102 (State 2 → state 3)
• NOP instruction
• CPUM4 → 12 (State 3 → state 4)
Double-speed mode at on-chip oscillator: NOP ✕ 3
High-speed mode at on-chip oscillator: NOP ✕ 1
Middle-speed mode at on-chip oscillator: NOP 0
Fig. 48 State transition
Rev.1.04 2004.06.08 page 39 of 66
REJ03B0012-0104Z