M37544 Datasheet, PDF (10/68 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

7544 Group
On-going Routine
Interrupt request
(Note)
M (S) (PCH)
Execute JSR
Store Return Address
on Stack
(S) (S – 1)
M (S) (PCL)
(S) (S – 1)
Subroutine
Restore Return
Address
Execute RTS
(S) (S + 1)
(PCL) M (S)
(S) (S + 1)
(PCH) M (S)
M (S) (PCH)
(S) (S – 1)
M (S) (PCL)
Store Return Address
on Stack
(S) (S – 1)
M (S) (PS)
Store Contents of Processor
Status Register on Stack
(S) (S – 1)
Interrupt
Service Routine
Execute RTI
(S) (S + 1)
(PS) M (S)
I Flag “0” to “1”
Fetch the Jump Vector
Restore Contents of
Processor Status Register
(S) (S + 1)
(PCL) M (S)
(S) (S + 1)
Restore Return
Address
(PCH) M (S)
Note : The condition to enable the interrupt Interrupt enable bit is “1”
Interrupt disable flag is “0”
Fig. 10 Register push and pop at interrupt generation and subroutine call
Table 3 Push and pop instructions of accumulator or processor status register
Push instruction to stack
Accumulator
PHA
Processor status register
PHP
Pop instruction from stack
PLA
PLP
Rev.1.04 2004.06.08 page 10 of 66
REJ03B0012-0104Z