M37544 Datasheet, PDF (20/68 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

7544 Group
Interrupt request bit
Interrupt enable bit
Interrupt disable flag I
Fig. 19 Interrupt control
BRK instruction
Reset
Interrupt request
b7
b0 _{Interrupt edge selection register}
(INTEDGE : address 003A16, initial value : 0016)
INT0 interrupt edge selection bit
0 : Falling edge active
1 : Rising edge active
INT1 interrupt edge selection bit
0 : Falling edge active
1 : Rising edge active
Disable (returns “0” when read)
P00 key-on wakeup enable bit
0 : Key-on wakeup enabled
1 : Key-on wakeup disabled
b7
b0 _{Interrupt request register 1}
(IREQ1 : address 003C16, initial value : 0016)
Serial I/O receive interrupt request bit
Serial I/O transmit interrupt request bit
INT0 interrupt request bit
INT1 interrupt request bit
Key-on wake up interrupt request bit
CNTR0 interrupt request bit
CNTR1 interrupt request bit
Timer X interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
b7
b0 _{Interrupt request register 2}
(IREQ2 : address 003D16, initial value : 0016)
Disable (returns “0” when read)
Disable (returns “0” when read)
Timer A interrupt request bit
Disable (returns “0” when read)
A/D conversion interrupt request bit
Timer 1 interrupt request bit
Disable (returns “0” when read)
b7
b0 _{Interrupt control register 1}
(ICON1 : address 003E16, initial value : 0016)
Serial I/O receive interrupt enable bit
Serial I/O transmit interrupt enable bit
INT0 interrupt enable bit
INT1 interrupt enable bit
Key-on wake up interrupt enable bit
CNTR0 interrupt enable bit
CNTR1 interrupt enable bit
Timer X interrupt enable bit
b7
b0 _{Interrupt control register 2}
(ICON2 : address 003F16, initial value : 0016)
Disable (returns “0” when read)
Disable (returns “0” when read)
Timer A interrupt enable bit
Disable (returns “0” when read)
A/D conversion interrupt enable bit
Timer 1 interrupt enable bit
Disable (returns “0” when read)
(Do not write “1” to this bit)
Fig. 20 Structure of Interrupt-related registers
0 : No interrupt request issued
1 : Interrupt request issued
0 : Interrupts disabled
1 : Interrupts enabled
0 : Interrupts disabled
1 : Interrupts enabled
Rev.1.04 2004.06.08 page 20 of 66
REJ03B0012-0104Z