M37544 Datasheet, PDF (19/68 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

7544 Group
Interrupts
Interrupts occur by 12 different sources : 5 external sources, 6 in-
ternal sources and 1 software source.
Interrupt control
All interrupts except the BRK instruction interrupt have an interrupt
request bit and an interrupt enable bit, and they are controlled by
the interrupt disable flag. When the interrupt enable bit and the in-
terrupt request bit are set to “1” and the interrupt disable flag is set
to “0”, an interrupt is accepted.
The interrupt request bit can be cleared by program but not be set.
The interrupt enable bit can be set and cleared by program.
The reset and BRK instruction interrupt can never be disabled with
any flag or bit. All interrupts except these are disabled when the
interrupt disable flag is set.
When several interrupts occur at the same time, the interrupts are
received according to priority.
Interrupt operation
Upon acceptance of an interrupt the following operations are auto-
matically performed:
1. The processing being executed is stopped.
2. The contents of the program counter and processor status reg-
ister are automatically pushed onto the stack.
3. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
4. Concurrently with the push operation, the interrupt destination
address is read from the vector table into the program counter.
[Interrupt edge selection register] INTEDGE
The valid edge of external interrupt INT0 and INT1 can be selected
by the interrupt edge selection bit, respectively.
By the key-on wakeup selection bit, enable/disable of a key-on
wakeup of P00 pin can be selected.
■ Notes on use
When setting the followings, the interrupt request bit may be set to
“1”.
•When setting external interrupt active edge
Related register: Interrupt edge selection register (address
003A16)
Timer X mode register (address 2B16)
Timer A mode register (address 1D16)
When not requiring the interrupt occurrence synchronized with
these setting, take the following sequence.
➀ Set the corresponding interrupt enable bit to “0” (disabled).
➁ Set the interrupt edge select bit (active edge switch bit) to “1”.
➂ Set the corresponding interrupt request bit to “0” after 1 or more
instructions have been executed.
➃ Set the corresponding interrupt enable bit to “1” (enabled).
Table 6 Interrupt vector address and priority
Vector addresses (Note 1)
Interrupt source Priority _{High-order Low-order}
Interrupt request generating conditions
Remarks
Reset (Note 2)
1
Serial I/O receive
2
Serial I/O transmit
3
INT0
4
INT1
5
Key-on wake-up
6
CNTR0
7
CNTR1
8
Timer X
9
Reserved area
—
Reserved area
—
Timer A
10
Reserved area
—
A/D conversion
11
Timer 1
12
Reserved area
—
BRK instruction
13
FFFD16
FFFB16
FFF916
FFF716
FFF516
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFE916
FFE716
FFE516
FFE316
FFE116
FFDF16
FFDD16
FFFC16
FFFA16
FFF816
FFF616
FFF416
FFF216
FFF016
FFEE16
FFEC16
FFEA16
FFE816
FFE616
FFE416
FFE216
FFE016
FFDE16
FFDC16
At reset input
At completion of serial I/O data receive
At completion of serial I/O transmit shift or
when transmit buffer is empty
At detection of either rising or falling edge of
INT0 input
At detection of either rising or falling edge of
INT1 input
At falling of conjunction of input logical level
for port P0 (at input)
At detection of either rising or falling edge of
CNTR0 input
At detection of either rising or falling edge of
CNTR1 input
At timer X underflow
Not available
Not available
At timer A underflow
Not available
At completion of A/D conversion
At timer 1 underflow
Not available
At BRK instruction execution
Non-maskable
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt (valid at falling)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
STP release timer underflow
Non-maskable software interrupt
Note 1: Vector addressed contain internal jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
Rev.1.04 2004.06.08 page 19 of 66
REJ03B0012-0104Z