M37544 Datasheet, PDF (32/68 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

7544 Group
Watchdog Timer
The watchdog timer gives a means for returning to a reset status
when the program fails to run on its normal loop due to a runaway.
The watchdog timer consists of an 8-bit watchdog timer H and an
8-bit watchdog timer L, being a 16-bit counter.
Standard operation of watchdog timer
The watchdog timer stops when the watchdog timer control regis-
ter (address 003916) is not set after reset. Writing an optional
value to the watchdog timer control register (address 003916)
causes the watchdog timer to start to count down. When the
watchdog timer H underflows, an internal reset occurs. Accord-
ingly, it is programmed that the watchdog timer control register
(address 003916) can be set before an underflow occurs.
When the watchdog timer control register (address 003916) is
read, the values of the high-order 6-bit of the watchdog timer H,
STP instruction disable bit and watchdog timer H count source se-
lection bit are read.
Initial value of watchdog timer
By a reset or writing to the watchdog timer control register (ad-
dress 003916), the watchdog timer H is set to “FF16” and the
watchdog timer L is set to “FF16”.
Operation of watchdog timer H count source selection bit
A watchdog timer H count source can be selected by bit 7 of the
watchdog timer control register (address 003916). When this bit is
“0”, the count source becomes a watchdog timer L underflow sig-
nal. The detection time is 131.072 ms at f(XIN)=8 MHz.
When this bit is “1”, the count source becomes f(XIN)/16. In this
case, the detection time is 512 µs at f(XIN)=8 MHz.
This bit is cleared to “0” after reset.
Operation of STP instruction disable bit
When the watchdog timer is in operation, the STP instruction can
be disabled by bit 6 of the watchdog timer control register (ad-
dress 003916).
When this bit is “0”, the STP instruction is enabled.
When this bit is “1”, the STP instruction is disabled, and an inter-
nal reset occurs if the STP instruction is executed.
Once this bit is set to “1”, it cannot be changed to “0” by program.
This bit is cleared to “0” after reset.
Data bus
Write “FF16” to the
watchdog timer
control register
“0”
Write "FF16" to the
watchdog timer
Watchdog timer L (8)
control register
XIN
1/16
“1”
Watchdog timer H (8)
Watchdog timer H count
source selection bit
STP Instruction disable bit
STP Instruction
RESET
Fig. 35 Block diagram of watchdog timer
Reset
circuit
Internal
reset
b7
b0
Watchdog timer control register
(WDTCON: address 003916, initial value: 3F16)
Watchdog timer H (read only for high-order 6-bit)
STP instruction disable bit
0 : STP instruction enabled
1 : STP instruction disabled
Watchdog timer H count source selection bit
0 : Watchdog timer L underflow
1 : f(XIN)/16
Fig. 36 Structure of watchdog timer control register
Rev.1.04 2004.06.08 page 32 of 66
REJ03B0012-0104Z