M37544 Datasheet, PDF(28/68 Page) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

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M37544 Datasheet, PDF (28/68 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

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7544 Group

(2) Asynchronous Serial I/O (UART) Mode

Clock asynchronous serial I/O mode (UART) can be selected by

clearing the serial I/O mode selection bit of the serial I/O control

Eight serial data transfer formats can be selected, and the transfer

formats used by a transmitter and receiver must be identical.

The transmit and receive shift registers each have a buffer, but the

two buffers have the same address in memory. Since the shift reg-

ister cannot be written to or read from directly, transmit data is

written to the transmit buffer register, and receive data is read

from the receive buffer register.

The transmit buffer register can also hold the next data to be

transmitted, and the receive buffer register can hold a character

while the next character is being received.

P10/RXD

P12/SCLK

XIN

P11/TXD

Data bus

Address 001816

Serial I/O control register Address 001A16

Receive buffer register

Character length selection bit

ST detector 7 bits

Receive shift register

8 bits

Receive buffer full flag (RBF)

Receive interrupt request (RI)

1/16

PE FE SP detector

Clock control circuit

UART control register

Address 001B16

Serial I/O synchronous clock selection bit

BRG count source selection bit

1/4

Frequency division ratio 1/(n+1)

Baud rate generator

Address 001C16

ST/SP/PA generator

1/16

Transmit shift completion flag (TSC)

Character length selection bit

Transmit shift register

Transmit interrupt source selection bit

Transmit interrupt request (TI)

Transmit buffer register

Address 001816

Transmit buffer empty flag (TBE)

Serial I/O status register Address 001916

Data bus

Fig. 30 Block diagram of UART serial I/O

Transmit or receive clock

Transmit buffer write

signal

Serial output TXD

TBE=0

TSC=0

TBE=1

Receive buffer read

signal

TBE=0

1 start bit

7 or 8 data bit

1 or 0 parity bit

1 or 2 stop bit (s)

Serial input RXD

TBE=1

TSC=1â½

â½

Generated at 2nd bit in 2-stop-bit mode

RBF=1

RBF=0

RBF=1

Notes 1: Error flag detection occurs at the same time that the RBF flag becomes â1â (at 1st stop bit, during reception).

2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes â1,â can be selected to occur depending on the setting of the transmit

interrupt source selection bit (TIC) of the serial I/O control register.

3: The receive interrupt (RI) is set when the RBF flag becomes â1.â

4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.

Fig. 31 Operation of UART serial I/O function

Rev.1.04 2004.06.08 page 28 of 66

REJ03B0012-0104Z

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