H8S2125 Datasheet, PDF (342/700 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series

Section 14 Watchdog Timer (WDT)
14.3.2 Timer Control/Status Register (TCSR)
TCSR selects the clock source to be input to TCNT, and the timer mode.
• TCSR_0
Initial
Bit Bit Name Value R/W Description
7
OVF
0
R/(W)* Overflow Flag
Indicates that TCNT has overflowed (changes from H'FF to
H'00).
[Setting condition]
When TCNT overflows (changes from H'FF to H'00)
When internal reset request generation is selected in
watchdog timer mode, OVF is cleared automatically by the
internal reset.
[Clearing conditions]
• When TCSR is read when OVF = 1, then 0 is written to
OVF
6
WT/IT 0
• When 0 is written to TME
R/W Timer Mode Select
Selects whether the WDT is used as a watchdog timer or
interval timer.
0: Interval timer mode
1: Watchdog timer mode
5
TME
0
R/W Timer Enable
When this bit is set to 1, TCNT starts counting.
When this bit is cleared, TCNT stops counting and is
initialized to H'00.
4

0
R/W Reserved
3
RST/NMI 0
The initial value should not be changed.
R/W Reset or NMI
Selects to request an internal reset or an NMI interrupt when
TCNT has overflowed.
0: An NMI interrupt is requested
1: An internal reset is requested
Rev. 1.00 Sep. 21, 2006 Page 304 of 658
REJ09B0310-0100