H8S2125 Datasheet, PDF (213/700 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series

Section 8 I/O Ports
8.6.2 Port 6 Data Register (P6DR)
P6DR stores output data for port 6.
Initial
Bit Bit Name Value R/W Description
7
P67DR
0
6
P66DR
0
5
P65DR
0
4
P64DR
0
R/W If a port 6 read is performed while P6DDR bits are set to
R/W ^{1, the P6DR values are read directly, regardless of the}
actual pin states. If a port 6 read is performed while
R/W _{P6DDR bits are cleared to 0, the pin states are read.}
R/W
3
P63DR
0
R/W
2
P62DR
0
R/W
1
P61DR
0
R/W
0
P60DR
0
R/W
8.6.3 Port 6 Noise Canceller Enable Register (P6NCE)
P6NCE specifies enable or disable for noise cancel circuit for the pins of port 6 on a bit-by-bit
basis.
Initial
Bit Bit Name Value R/W Description
7
P67NCE 0
6
P66NCE 0
5
P65NCE 0
R/W Noise cancel circuit is enabled when P6NCCS bit is set
R/W ^{to 1, and the pin state is fetched in the P6DR in the}
sampling cycle set by the P6NCCS.
R/W
4
P64NCE 0
R/W
3
P63NCE 0
R/W
2
P62NCE 0
R/W
1
P61NCE 0
R/W
0
P60NCE 0
R/W
Rev. 1.00 Sep. 21, 2006 Page 175 of 658
REJ09B0310-0100