M16C30L Datasheet, PDF (31/166 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Bus Control
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
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(5) The RDY signal
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RDY is a signal that facilitates access to an external device that requires long access time. As shown in
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Figure 1.9.4, if an “L” is being input to the RDY at the BCLK falling edge, the bus turns to the wait state. If
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an “H” is being input to the RDY pin at the BCLK falling edge, the bus cancels the wait state. Table 1.9.5
shows the state of the microcomputer with the bus in the wait state, and Figure 1.9.4 shows an example
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in which the RD signal is prolonged by the RDY signal.
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The RDY signal is valid when accessing the external area during the bus cycle in which bits 4 to 7 of the
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chip select control register (address 000816) are set to “0”. The RDY signal is invalid when setting “1” to
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all bits 4 to 7 of the chip select control register (address 000816), but the RDY pin should be treated as
properly as in non-using.
Table 1.9.5. Microcomputer status in wait state (Note)
Item
Status
Oscillation
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R/W signal, address bus, data bus, CS
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ALE signal, HLDA, programmable I/O ports
On
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Maintain status when RDY signal received
Internal peripheral circuits
On
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Note: The RDY signal cannot be received immediately prior to a software wait.
In an instance of separate bus
BCLK
RD
CSi
(i=0 to 3)
RDY
tsu(RDY - BCLK)
Accept timing of RDY signal
In an instance of multiplexed bus
BCLK
RD
CSi
(i=0 to 3)
RDY
: Wait using RDY signal
: Wait using software
tsu(RDY - BCLK)
Accept timing of RDY signal
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Figure 1.9.4. Example of RD signal extended by RDY signal
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