M16C30L Datasheet, PDF (156/166 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Electrical characteristics
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Switching characteristics (referenced to VCC = 3.3V, VSS = 0V at Topr = – 20^oC to 85^oC / – 40^oC to
85^oC (Note 2), CM15 = “1” unless otherwise specified)
Table 1.26.23. Memory expansion and microprocessor modes
(when accessing external memory area with wait, and select multiplexed bus)
Symbol
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
th(WR-AD)
Parameter
Address output delay time
Address output hold time (BCLK standard)
Address output hold time (RD standard)
Address output hold time (WR standard)
Measuring condition
Standard
Min. Max.
50
4
(Note1)
(Note1)
Unit
ns
ns
ns
ns
td(BCLK-CS) Chip select output delay time
50
ns
th(BCLK-CS) Chip select output hold time (BCLK standard)
4
ns
th(RD-CS)
th(WR-CS)
Chip select output hold time (RD standard)
Chip select output hold time (WR standard)
(Note1)
ns
(Note1)
ns
td(BCLK-RD) RD signal output delay time
40
ns
th(BCLK-RD) RD signal output hold time
td(BCLK-WR) WR signal output delay time
Figure 1.26.1 ⁰
ns
40
ns
th(BCLK-WR) WR signal output hold time
td(BCLK-DB) Data output delay time (BCLK standard)
0
ns
50
ns
th(BCLK-DB)
td(DB-WR)
th(WR-DB)
td(BCLK-ALE)
th(BCLK-ALE)
td(AD-ALE)
Data output hold time (BCLK standard)
Data output delay time (WR standard)
Data output hold time (WR standard)
ALE signal output delay time (BCLK standard)
ALE signal output hold time (BCLK standard)
ALE signal output delay time (Address standard)
4
ns
(Note1)
ns
(Note1)
ns
40
ns
–4
ns
(Note1)
ns
th(ALE-AD)
td(AD-RD)
ALE signal output hold time (Adderss standard)
Post-address RD signal output delay time
td(AD-WR)
tdZ(RD-AD)
Post-address WR signal output delay time
Address output floating start time
Note 1: Calculated according to the BCLK frequency as follows:
30
ns
0
ns
0
ns
8
ns
10 ⁹
th(RD – AD) =
+0
f(BCLK) X 2
[ns]
th(WR – AD) =
10 ⁹
+0
f(BCLK) X 2
[ns]
th(RD – CS) =
10 ⁹
+0
f(BCLK) X 2
[ns]
10 ⁹
th(WR – CS) =
+0
f(BCLK) X 2
[ns]
td(DB – WR) =
10 ^{9 X 3}
f(BCLK) X 2 ^{– 50} [ns]
10 ⁹
th(WR – DB) =
+0
f(BCLK) X 2
[ns]
10 ⁹
td(AD – ALE) = _{f(BCLK) X 2 – 40 [ns]}
Note 2: Specify a product of -40°C to 85°C to use it.
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