English
Language : 

NP35N04YLG Datasheet, PDF (2/8 Pages) Renesas Technology Corp – MOS FIELD EFFECT TRANSISTOR
NP35N04YLG
Chapter Title
Electrical Characteristics (TA = 25°C)
Item
Symbol Min
Zero Gate Voltage Drain Current IDSS
Gate Leakage Current
IGSS
Gate to Source Threshold Voltage VGS(th)
1.4
Forward Transfer Admittance ∗1
| yfs |
15
Drain to Source On-state
Resistance ∗1
RDS(on)1
Drain to Source On-state
Resistance ∗1
RDS(on)2
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Turn-on Delay Time
td(on)
Rise Time
tr
Turn-off Delay Time
td(off)
Fall Time
tf
Total Gate Charge
QG
Gate to Source Charge
QGS
Gate to Drain Charge
Body Diode Forward Voltage ∗1
QGD
VF(S-D)
Reverse Recovery Time
trr
Reverse Recovery Charge
Qrr
Note: ∗1. Pulsed
Typ
1.9
30
7.8
9.6
1900
190
120
13
11
43
5
34
6
10
0.91
27
25
Max
1
±10
2.5
9.7
15
2850
290
220
26
27
86
12
51
1.5
Unit
μA
μA
V
S
mΩ
mΩ
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
ns
nC
Test Conditions
VDS = 40 V, VGS = 0 V
VGS = ±20 V, VDS = 0 V
VDS = VGS, ID = 250 μ A
VDS = 5 V, ID = 17.5 A
VGS = 10 V, ID = 17.5 A
VGS = 5 V, ID = 17.5 A
VDS = 25 V,
VGS = 0 V,
f = 1 MHz
VDD = 20 V, ID = 17.5 A,
VGS = 10 V,
RG = 0 Ω
VDD = 32 V,
VGS = 10 V,
ID = 35 A
IF = 35 A, VGS = 0 V
IF = 35 A, VGS = 0 V,
di/dt = 100 A/μ s
TEST CIRCUIT 1 AVALANCHE CAPABILITY
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG = 25 Ω
L
PG.
50 Ω
VDD
VGS = 20 → 0 V
IAS
ID
VDD
BVDSS
VDS
Starting Tch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
PG.
RG
VGS
0
τ
τ = 1 μs
Duty Cycle ≤ 1%
RL
VDD
VGS
VGS
Wave Form
10%
0
VDS
90%
VDS
VDS
0
Wave Form
td(on)
VGS
90%
90%
10% 10%
tr td(off)
tf
ton
toff
D.U.T.
IG = 2 mA
RL
PG.
50 Ω
VDD
R07DS0182EJ0100 Rev.1.00
Oct 22, 2010
Page 2 of 6