NP119N04NUK Datasheet, PDF (2/8 Pages) Renesas Technology Corp – N-channel Power MOS FET

NP119N04NUK
Preliminary
Electrical Characteristics (TA = 25°C)
Item
Zero Gate Voltage Drain Current
Gate Leakage Current
Gate to Source Threshold Voltage
Forward Transfer Admittance ^*1
Drain to Source On-state Resistance ^*1
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
Total Gate Charge
Gate to Source Charge
Gate to Drain Charge
Body Diode Forward Voltage ^*1
Reverse Recovery Time
Reverse Recovery Charge
Note: *1 Pulsed test
Symbol
IDSS
IGSS
VGS(th)
| yfs |
RDS(on)
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
QG
QGS
QGD
VF(S-D)
trr
Qrr
MIN.
—
—
2.0
50
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TYP.
—
—
3.0
114
1.80
7400
1000
390
30
11
105
13
130
32
31
0.9
56
80
MAX.
1
±100
4.0
—
2.15
11100
1500
710
70
30
210
40
195
—
—
1.5
—
—
Unit
μA
nA
V
S
mΩ
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
ns
nC
Test Conditions
VDS = 40 V, VGS = 0 V
VGS = ±20 V, VDS = 0 V
VDS = VGS, ID = 250 μA
VDS = 5 V, ID = 60 A
VGS = 10 V, ID = 60 A
VDS = 25 V
VGS = 0 V
f = 1 MHz
VDD = 20 V, ID = 60 A
VGS = 10 V
RG = 0 Ω
VDD = 32 V
VGS = 10 V
ID = 120 A
IF = 120 A, VGS = 0 V
IF = 120 A, VGS = 0 V
di/dt = 100 A/μs
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
R_G = 25 Ω
L
PG.
V_GS = 20 → 0 V
50 Ω
V_DD
BV_DSS
I_D ^IAS
V_DD
V_DS
Starting T_ch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
I_G = 2 mA
R_L
PG.
50 Ω
V_DD
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
PG.
R_G
V_GS
0
τ
τ = 1 μs
Duty Cycle ≤ 1%
R_L
V_GS
V_GS
Wave Form
10%
0
V_DD
V_DS
90%
V_DS
V_DS
0
Wave Form
t_d(on)
V_GS
90%
90%
10% 10%
t_r t_d(off)
t_f
t_on
t_off
R07DS1252EJ0100 Rev.1.00
Mar 30, 2015
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