NE5550279A Datasheet, PDF (2/9 Pages) Renesas Technology Corp – Silicon Power LDMOS FET

NE5550279A
RECOMMENDED OPERATING RANGE (T_A = 25°C)
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current
Input Power
Symbol
V_DS
V_GS
I_DS
P_in
Test Conditions
f = 460 MHz, V_DS = 7.5 V
MIN.
−
1.65
−
−
TYP.
7.5
2.20
0.4
15
MAX.
9.0
2.85
−
20
Unit
V
V
A
dBm
ELECTRICAL CHARACTERISTICS (T_A = 25°C, unless otherwise specified)
Parameter
DC Characteristics
Gate to Source Leakage Current
Drain to Source Leakage Current
(Zero Gate Voltage Drain Current)
Gate Threshold Voltage
Drain to Source Breakdown Voltage
Transconductance
Thermal Resistance
RF Characteristics
Output Power
Drain Current
Power Drain Efficiency
Power Added Efficiency
Linear Gain
Note: P_in = 0 dBm
Symbol
I_GSS
I_DSS
V_th
BV_DSS
G_m
R_th
P_out
I_DS
η_d
η_add
G_L ^Note
Test Conditions
V_GS = 6.0 V
V_DS = 25 V
V_DS = 7.5 V, I_DS = 1.0 mA
I_DS = 10 μA
V_DS = 7.5 V, I_DS = 100±100 mA
Channel to Case
f = 460 MHz, V_DS = 7.5 V,
P_in = 15 dBm,
I_Dset = 40 mA (RF OFF)
MIN.
−
−
1.15
25
1.8
−
31.5
−
−
−
−
TYP. MAX.
−
100
−
10
1.65 2.25
38
−
2.2
2.9
20.0
−
33.0
−
0.38
−
70
−
68
−
22.5
−
Unit
nA
μA
V
V
S
°C/W
dBm
A
%
%
dB
Remark DC performance is 100% testing. RF performance is testing several samples per wafer.
Wafer rejection criteria for standard devices is 1 reject for several samples.
R09DS0033EJ0100 Rev.1.00
Mar 28, 2012
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