M16C62 Datasheet, PDF (121/231 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

UART2 Special Mode Register 2
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
P70/TXD2/SDA
P71/RXD2/SCL
P72/CLK2
Timer
Selector
I/0
UART2
IICM=1
delay
IICM=0
SDHI _ALS
Transmission register
UART2
IICM=0
or
IICM2=1
IICM=1
and IICM2=0
To DMA0, DMA1
UART2 transmission/
NACK interrupt
request
DQ
Arbitration
To DMA0
Noize
Filter
T
IICM=1
IICM=0
or IICM2=1
UART2 reception/ACK interrupt request
DMA1 request
Reception register
IICM=0
Start condition detection
UART2
IICM=1
and IICM2=0
Stop condition detection
S
Bus
Q
R
busy
Falling edge
detection
L-synchronous
output enabling bit
DQ
T
NACK
I/0
R
Data register
DQ
T
ACK
Noize
Filter
Noize
Filter
Selector
UART2
IICM=1
IICM=1
IICM=0
9th pulse
Internal clock
SWC2
External clock
CLK
control
Bus collision
detection
UART2
IICM=1 ^{Bus collision/start, stop condition detection}
interrupt request
IICM=0
R
Falling of 9th pulse
S
SWC
UART2
IICM=0
Selector
I/0
Timer
Port reading
* With IICM set to 1, the port terminal is to be readable
even if 1 is assigned to P71 of the direction register.
Note: P72/CLK2 is not connected to the outside.
Figure 1.14.30. Functional block diagram for I²C mode
Functions available in I²C mode are shown in Figure 1.14.30 — a functional block diagram.
Bit 3 of the UART2 special mode register 2 (address 037616) is used as the SDA output stop bit. Setting
this bit to "1" causes an arbitration loss to occur, and the SDA pin turns to high-impedance state the
instant when the arbitration loss detection flag is set to "1".
Bit 1 of the UART2 special mode register 2 (address 037616) is used as the clock synchronization bit.
With this bit set to "1" at the time when the internal SCL is set to "H", the internal SCL turns to "L" if the
falling edge is found in the SCL pin; and the baud rate generator reloads the set value, and start counting
within the "L" interval. When the internal SCL changes from "L" to "H" with the SCL pin set to "L", stops
counting the baud rate generator, and starts counting it again when the SCL pin turns to "H". Due to this
function, the UART2 transmission-reception clock becomes the logical product of the signal flowing
through the internal SCL and that flowing through the SCL pin. This function operates over the period
from the moment earlier by a half cycle than falling edge of the UART2 first clock to the rising edge of the
ninth bit. To use this function, choose the internal clock for the transfer clock.
Bit 2 of the UART2 special mode register 2 (037616) is used as the SCL wait output bit. Setting this bit to
"1" causes the SCL pin to be fixed to "L" at the falling edge of the ninth bit of the clock. Setting this bit to
"0" frees the output fixed to "L".
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