TMS320TCI6487 Datasheet, PDF (11/206 Pages) Texas Instruments – Communications Infrastructure Digital Signal Processor

www.ti.com
Data path A
Data path B
TMS320TCI6487
TMS320TCI6488
Communications Infrastructure Digital Signal Processor
SPRS358F – APRIL 2007 – REVISED AUGUST 2008
ST1b ^{32 MSB}
ST1a ^{32 LSB}
LD1b ^{32 MSB}
LD1a ^{32 LSB}
DA1
src1
.L1
src2
odd dst
even dst
long src
8
long src
8
even dst
odd dst
src1
.S1
src2
dst2
.M1
dst1
src1
32
32
src2
dst
.D1 src1
src2
DA2
LD2a ^{32 LSB}
LD2b ^{32 MSB}
ST2a ^{32 MSB}
ST2b ^{32 LSB}
src2
.D2 _src1
dst
src2
.M2 _src1
dst2
32
dst1 ³²
src2
.S2
src1
odd dst
even dst
long src
8
long src
8
even dst
odd dst
src2
.L2
src1
Odd
register
fileA
(A1, A3,
A5...A31)
(D)
Even
register
file A
(A0, A2,
A4...A30)
(D)
(A)
(B)
(C)
2x
1x
Odd
register
file B
(B1, B3,
B5...B31)
Even
register
file B
(B0, B2,
B4...B30)
(C)
(B)
(A)
(D)
(D)
Control Register
A. On .M unit, dst2 is 32 MB.
B. On .M unit, dst1 is 32 LSB.
C. On 64x+ CPU .M unit, src2 is 32 bits; on C64x+ CPU .M unit, src2 is 64 bits.
D. On .L and .S units, odd dst connects to odd register files and even dst connects to even register files.
Figure 2-1. TMS320C64x+TM CPU (DSP Core) Data Path
Submit Documentation Feedback
Device Overview
11