TMS320TCI6487 Datasheet, PDF (102/206 Pages) Texas Instruments – Communications Infrastructure Digital Signal Processor

TMS320TCI6487
TMS320TCI6488
Communications Infrastructure Digital Signal Processor
SPRS358F – APRIL 2007 – REVISED AUGUST 2008
www.ti.com
8.5 Interrupts
8.5.1 Interrupt Sources and Interrupt Controller
The CPU interrupts on the device are configured through the C64x+ Megamodule Interrupt Controller. The
interrupt controller allows for up to 128 system events to be programmed to any of the twelve CPU
interrupt inputs, the CPU exception input, or the advanced emulation logic. Table 8-11 shows the mapping
of system events to the interrupt controller inputs. Event numbers 0-31 correspond to the default interrupt
mapping of the device. The remaining events must be mapped using software. For more details on Chip
Interrupt Controller 0-2 (CIC0, CIC1, and CIC2), see Section 8.5.2.
Table 8-11. Interrupts
EVENT CHANNEL
EVENT
EVENT DESCRIPTION
0
EVT0
Output of Event Combiner 0 for Events [31:4]
1
EVT1
Output of Event Combiner 1 for Events [63:32]
2
EVT2
Output of Event Combiner 2 for Events [95:64]
3
EVT3
Output of Event Combiner 3 for Events [127:96]
4
SEMINTn ⁽¹⁾
Semaphore Grant Interrupt
5
MACINTn ⁽²⁾
Ethernet MAC Control Interrupt
6
MACRXINTn ⁽²⁾
Ethernet MAC Receive Interrupt
7
MACTXINTn ⁽²⁾
Ethernet MAC Transmit Interrupt
8
MACTHRESHn ⁽²⁾
Ethernet MAC Receive Threshold Interrupt
9
EMU_DTDMA
ECM Interrupt for:
1. Host Scan Access
2. DTDMA Transfer Complete
3. AET Interrupt
10
RAC INTn⁽³⁾
RAC Interrupt N
11
EMU_RTDXRX
RTDX Receive Complete
12
EMU_RTDXTX
RTDX Transmit Complete
13
IDMAINT0
IDMA Channel 0 Interrupt
14
IDMAINT1
IDMA Channel 1 Interrupt
15
FSEVT0
Frame Synchronization Event 0
16
FSEVT1
Frame Synchronization Event 1
17
FSEVT2
Frame Synchronization Event 2
18
FSEVT3
Frame Synchronization Event 3
19
FSEVT4
Frame Synchronization Event 4
20
FSEVT5
Frame Synchronization Event 5
21
FSEVT6
Frame Synchronization Event 6
22
FSEVT7
Frame Synchronization Event 7
23
FSEVT8
Frame Synchronization Event 8
24
FSEVT9
Frame Synchronization Event 9
25
FSEVT10
Frame Synchronization Event 10
26
FSEVT11
Frame Synchronization Event 11
27
FSEVT12
Frame Synchronization Event 12
28
FSEVT13
Frame Synchronization Event 13
29
FSEVT14
Frame Synchronization Event 14
(1) C64x+ Megamodule Core 0, C64x+ Megamodule Core 1, and C64x+ Megamodule Core 2 receive SEMINT0, SEMINT1, and SEMINT2,
respectively.
(2) EMAC interrupts, MACINTn, MACRXINTn, MACTXINTn, and MACTHRESHn are received by the C64x+ Megamodules, as follows:
• C64x+ Megamodule Core 0 receives MACINT[0], MACRXINT[0], MACTXINT[0], and MACTHRESH[0]
• C64x+ Megamodule Core 1 receives MACINT[1], MACRXINT[1], MACTXINT[1], and MACTHRESH[1]
• C64x+ Megamodule Core 2 receives MACINT[2], MACRXINT[2], MACTXINT[2], and MACTHRESH[2]
(3) C64x+ Megamodule Core 0, C64x+ Megamodule Core 1, and C64x+ Megamodule Core 2 receive RACINT0, RACINT1, and RACINT2,
respectively.
102 Peripheral Information and Electrical Specifications
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