TMS320TCI6487 Datasheet, PDF (1/206 Pages) Texas Instruments – Communications Infrastructure Digital Signal Processor

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TMS320TCI6487
TMS320TCI6488
Communications Infrastructure Digital Signal Processor
SPRS358F – APRIL 2007 – REVISED AUGUST 2008
1 Features
• High-Performance Communications
Infrastructure DSP (TCI6487/8)
– 1-ns Instruction Cycle Time
– 1.0-GHz Clock Rate
– Eight 32-Bit Instructions/Cycle
– Commercial Temperature 0°C to 100°C
• 3 TMS320C64x+™ DSP Cores
– Dedicated SPLOOP Instructions
– Compact Instructions (16-Bit)
– Exception Handling
• TMS320C64x+ Megamodule L1/L2 Memory
Architecture
– 256 K-Bit (32 K-Byte) L1P Program Cache
[Direct Mapped]
– 256 K-Bit (32 K-Byte) L1D Data Cache
[2-Way Set-Associative]
– 24 M-Bit (3072 K-Byte) Total L2 Unified
Mapped RAM/Cache [Flexible Allocation]
• Configurable at boot-time to 1 MB/
1 MB/1 MB or 1.5 MB/1 MB/0.5 MB
– 512 K-Bit (64 K-Byte) L3 ROM
• One Receive Accelerator (RAC) [TCI6488 Only]
– Performs Chip-Rate RX Functions
– Up to 64 Macro-BTS Users
– Up to 160 km cell size
• Six RSAs for CDMA Processing (2 per core)
– Dedicated RAKE, PATH_SEARCH and
RACH_SEARCH Instructions
– Transmit Processing Capability
• Enhanced VCP2
– Supports Over 694 7.95-Kbps AMR
• Enhanced Turbo Decoder Coprocessor (TCP2)
– Supports up to Eight 2-Mbps 3 GPP
(6 Iterations)
• Endianness: Little Endian, Big Endian
• Frame Synchronization Interface
– Time Alignment Between Internal
Subsystems, External Devices/System
– OBSAI RP1 Compliant for Frame Burst Data
– Alternate Interfaces for non-RP1 and
non-UMTS Systems
• 16-/32-Bit DDR2-667 Memory Controller
• EDMA3 Controller (64 Independent Channels)
• Antenna Interface
– 6 Configurable Links (Full Duplex)
– Supports OBSAI RP3 Protocol, v1.0
– 768-Mbps, 1.536-, 3.072-Gbps Link Rates
– Supports CPRI Protocol V2.0
– 614.4-Mbps, 1.2288-, 2.4576-Gbps Link
Rates
– Clock Input Independent or Shared with
CPU (Selectable at Boot-Time)
• Two 1x Serial RapidIO® Links, v1.2 Compliant
– 1.25-, 2.5-, 3.125-Gbps Link Rates
– Message Passing and DirectIO Support
– Error Management Extensions and
Congestion Control
• One 1.8-V Inter-Integrated Circuit (I2C) Bus
• Two 1.8-V McBSPs
• 1000 Mbps Ethernet MAC (EMAC)
– IEEE 802.3 Compliant
– Supports SGMII, v1.8 Compliant
– 8 Independent Transmit (TX) and 8
Independent Receive (RX) Channels
• Six 64-Bit General-Purpose Timers
– Configurable up to Twelve 32-Bit Timers
– Configurable in a Watchdog Timer mode
• 16 General-Purpose I/O (GPIO) Pins
• Internal Semaphore Module
– Software Method to Control Access to
Shared Resources
– 32 General Purpose Semaphore Resources
• System PLL and PLL Controller
• DDR PLL and PLL Controller, Dedicated to
DDR2 Memory Controller
• Supports IP Security
• IEEE-1149.1 and IEEE-1149.6 (JTAG™)
Boundary-Scan-Compatible
• 561-Pin Ball Grid Array (BGA) Packages (CUN,
GUN, or ZUN Suffix), 0.8-mm Ball Pitch
• 0.065-µm/7-Level Cu Metal Process (CMOS)
• SmartReflex™ Class 0 Enabled - 0.9-V to 1.2-V
Adaptive Core Voltage
• 1.8-V, 1.1-V I/Os
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Instruments semiconductor products and disclaimers thereto appears at the end of this document.
TMS320C64x+, SmartReflex, TMS320C6000, VelociTI, C64x+, C6000, Code Composer Studio, DSP/BIOS, XDS are trademarks of Texas
Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2008, Texas Instruments Incorporated