HYB39S512400AT Datasheet, PDF (9/21 Pages) Infineon Technologies AG – 512-Mbit Synchronous DRAM

Internet Data Sheet
HY[I/B]39S512[40/80/16]0A[E/T]
512-Mbit Synchronous DRAM
3
Functional Description
This chapter lists all defined commands and their usage for this Synchronous DRAM family.
TABLE 4
Truth Table: Operation Command
Operation
Device State
CKE
n-1¹⁾²⁾
CKE
n¹⁾²⁾
DQM BA0 AP= Addr. CS RAS CAS WE
1)2)
BA1¹⁾²⁾ A10^{1)2) 1)2)}
1)2) 1)2)
1)2)
1)2)
Bank Active
Idle³⁾
H
X
X
V
V
V
LL H H
Bank Precharge
Any
H
X
X
V
L
X
LL H L
Precharge All
Write
Write with Auto
precharge
Read
Read with Auto
precharge
Any
Active³⁾
Active³⁾
Active³⁾
Active³⁾
H
X
X
X
H
X
LL H L
H
X
X
V
L
V
LH L L
H
X
X
V
H
V
LH L L
H
X
X
V
L
V
LH L H
H
X
X
V
H
V
LH L H
Mode Register Set Idle
H
X
X
V
V
V
LL L L
No Operation
Any
H
X
X
X
X
X
LH H H
Burst Stop
Active
H
X
X
X
X
X
LH H L
Device Deselect
Any
H
X
X
X
X
X
HX X X
Auto Refresh
Idle
H
H
X
X
X
X
LL L H
Self Refresh Entry Idle
H
L
X
X
X
X
LL L H
Self Refresh Exit
Idle (Self Refr.) L
H
X
X
X
X
HX X X
LH H X
Power Down/
Active or Idle
H
Clock Suspend Entry or Burst
L
X
X
X
X
HX X X
LH H H
Power Down/
Active or Idle
L
Clock Suspend Exit or Burst
H
X
X
X
X
HX X X
LH H H
Data Write/
Output Enable
Active
H
X
L
X
X
X
XX X X
Data Write/
Output Disable
Active
H
X
H
X
X
X
XX X X
1) V = Valid, x = Don’t Care, L = Low Level, H = High Level
2) CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands are provided.
3) This is the state of the banks designated by BA0, BA1 signals.
Rev. 1.52, 2007-06
9
03292006-6Y91-0T2Z