HYB39S512400AT Datasheet, PDF (13/21 Pages) Infineon Technologies AG – 512-Mbit Synchronous DRAM

Internet Data Sheet
HY[I/B]39S512[40/80/16]0A[E/T]
512-Mbit Synchronous DRAM
TABLE 8
DC Characteristics
Parameter
Symbol
Values
Min. Max.
Unit Note/
Test Condition
Supply Voltage
V_DD
3.0 3.6
V
1)
I/O Supply Voltage
V_DDQ 3.0 3.6
V
1)
Input high voltage
V_IH
2.0 V_DDQ + 0.3 V ¹⁾²⁾
Input low voltage
V_IL
–0.3 +0.8
V
1)2)
Output high voltage (I_OUT = – 4.0 mA)
V_OH
2.4 —
V
1)
Output low voltage (I_OUT = 4.0 mA)
V_OL
— 0.4
V
1)
Input leakage current, any input (0 V < V_IN < V_DD, all other inputs = 0 V) I_IL
–5 +5
µA —
Output leakage current (DQs are disabled, 0 V < V_OUT < V_DDQ)
I_OL
–5 +5
µA —
1) All voltages are referenced to V_SS
2) V_IH may overshoot to V_DDQ + 2.0 V for pulse width of < 4ns with 3.3 V. V_IL may undershoot to -2.0 V for pulse width < 4.0 ns with 3.3 V.
Pulse width measured at 50% points with amplitude measured peak to DC reference.
Parameter
TABLE 9
Input and Output Capacitances
Symbol Values
Unit Note
Min. Max.
Input Capacitances: CK
Input Capacitance
(A0-A12, BA0, BA1, RAS, CAS, WE, CS, CKE, DQM)
C_I1
2.5 3.5
pF
1)2)
C_I2
2.5 3.8
pF
1)2)
Input/Output Capacitance (DQ)
C_I0
4.0 6.0
pF
1)2)
1) V_DD,V_DDQ = 3.3 V ± 0.3 V, f = 1 MHz, T_A see Table 7
2) Capacitance values are shown for TSOP-54 packages. Capacitance values for TFBGA packages are lower by 0.5 pF
Rev. 1.52, 2007-06
13
03292006-6Y91-0T2Z