HYB39S512400AT Datasheet, PDF (2/21 Pages) Infineon Technologies AG – 512-Mbit Synchronous DRAM

Internet Data Sheet
HY[I/B]39S512[40/80/16]0A[E/T]
512-Mbit Synchronous DRAM
HY[B/I]39S512400A[E/T], HY[B/I]39S512800A[E/T], HY[B/I]39S512160A[E/T]
Revision History: 2007-06, Rev. 1.52
Page
Subjects (major changes since last revision)
All
Adapted internet edition
13
Corrected operation command "Power Down / Clock suspend ...” in truth table
Previous Revision: 2007-06, Rev. 1.51
13
Corrected operation command "Power Down Exit" to X (WE#)
15
Corrected text to "After the mode register is set a NOP command is required" , chapter 3.3
19
Corrected text to "One clock delay is required for mode entry and exit", chapter 3.5
21
Corrected the line "Input Capacitances: CK" in table 10, chapter 4
Qimonda template
Previous Revision: 2007-05, Rev. 1.5
All
Added more product types
Previous Revision: 2006-01, Rev. 1.4
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qag_techdoc_rev400 / 3.2 QAG / 2006-07-21
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03292006-6Y91-0T2Z