HYB39S512400AT Datasheet, PDF (5/21 Pages) Infineon Technologies AG – 512-Mbit Synchronous DRAM

Internet Data Sheet
2
Configuration
HY[I/B]39S512[40/80/16]0A[E/T]
512-Mbit Synchronous DRAM
This chapter contains the pin configuration table and the TSOP package drawing.
2.1
Pin Configuration
Listed below are the pin configurations sections for the various signals of the SDRAM.
TABLE 3
Ball Configuration of the SDRAM
Ball No. Name Pin Buffer
Type Type
Function
Clock Signals x4/ x8/ x16 Organization
38
CLK I
LVTTL Clock Signal CLK
37
CKE I
LVTTL Clock Enable
Control Signals x4/ x8/ x16 Organization
18
RAS I
LVTTL Row Address Strobe (RAS), Column Address Strobe (CAS), Write Enable (WE)
17
CAS I
LVTTL
16
WE I
LVTTL
19
CS
I
LVTTL Chip Select
Address Signals x4/ x8/ x16 Organization
20
BA0 I
LVTTL Bank Address Signals 1:0
21
BA1 I
LVTTL
23
A0
I
LVTTL Address Signal 9:0, Address Signal 10/Auto precharge
24
A1
I
LVTTL
25
A2
I
LVTTL
26
A3
I
LVTTL
29
A4
I
LVTTL
30
A5
I
LVTTL
31
A6
I
LVTTL
32
A7
I
LVTTL
33
A8
I
LVTTL
34
A9
I
LVTTL
22
A10 I
LVTTL
35
A11 I
LVTTL
36
A12 I
LVTTL
Rev. 1.52, 2007-06
5
03292006-6Y91-0T2Z