HYB18L512320BF-7.5 Datasheet, PDF (9/23 Pages) Qimonda AG – DRAMs for Mobile Applications 512-Mbit SDR Mobile-RAM

Internet Data Sheet
HY[B/E]18L512320BF-7.5
512-Mbit Mobile-RAM
Field Bits
BT 3
BL [2:0]
Type
w
w
Description
Burst Type
0 Sequential
1 Interleaved
Burst Length
000 1
001 2
010 4
011 8
111 full page (Sequential burst type only)
Note: All other bit combinations are RESERVED.
2.2
Extended Mode Register
The Extended Mode Register controls additional low power features of the device. These include the Partial Array Self Refresh
(PASR, bits A0-A2)), the Temperature Compensated Self Refresh (TCSR, bits A3-A4)) and the drive strength selection for the
DQs (bits A5-A6). The Extended Mode Register is programmed via the MODE REGISTER SET command (with BA0 = 0 and
BA1 = 1) and will retain the stored information until it is programmed again or the device loses power.
The Extended Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before
initiating any subsequent operation. Violating either of these requirements result in unspecified operation.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
EMR
Extended Mode Register(BA[1:0] = 10_B)
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7&65
3$65
03%/
Field
Bits
DS
[6:5]
TCSR [4:3]
PASR [2:0]
Type
w
w
w
Description
TABLE 6
Extended Mode Register Definition (BA[1:0] = 10_B)
Selectable Drive Strength
00_B DS Full Drive Strength
01_B DS Half Drive Strength
Note: All other bit combinations are RESERVED.
Temperature Compensated Self Refresh
XX Superseded by on-chip temperature sensor (see text)
Partial Array Self Refresh
000_B PASR all banks (default)
001_B PASR 1/2 array (BA1 = 0)
010_B PASR 1/4 array (BA1 = BA0 = 0)
101_B PASR 1/8 array (BA1 = BA0 = RA12 = 0)
110_B PASR 1/16 array (BA1 = BA0 = RA12 = RA11 = 0)
Note: All other bit combinations are RESERVED.
Rev.1.22, 2007-08
9
03292006-D7GM-ZBSS